Phase locked loops (PLL) are well known in the state of the art and essentially consist of; a phase comparator for receiving and comparing an external input signal to a voltage controlled oscillator (VCO) signal, a low pass filter for receiving the output of the phase comparator, and a VCO receiving the output of the low pass filter. Basically the phase comparator forms a difference signal by comparing the external input signal and the VCO signal. The difference signal is passed through a low pass filter to obtain a DC control voltage which controls the frequency of the VCO. When the frequency of the external input signal and the frequency of the voltage controlled oscillator are substantially identical, the phase locked loop is said to be in a state of lock. Conversely, when the external input signal and the VCO signal differ in frequency by more than a predetermined amount, the PLL is said to be in a state of unlock.
It is useful to determine when the phase locked loop is in a state of lock so that certain loop parameters can be changed to insure narrow loop tracking in order to reject noise and other interferring signals. However, when the phase locked loop is not in a state of lock wide loop tracking parameters are desired so that the loop can aquire lock over a wide frequency range. The concept of changing loop bandwidth in response to whether the phase locked loop is in a state of lock or not is known, as in U.S. Pat. No. 3,805,183. Several systems for changing phase locked loop parameters in response to a control system are described in U.S. Pat. No. 3,209,271. Prior art state of lock detectors sense the signal amplitude of the phase comparator output or the low pass filter output, to determine whether the phase locked loop is in a state of lock or unlock. However, if the input signals to the phase comparator are noisy or possess low frequency modulation, the prior art detection schemes will give erroneous readings as to whether the phase locked loop is in a state of lock.